1. Field of the Invention
The present invention relates to semiconductor memory devices, and more particularly, to an input/output sense amplifier which uses signals to vary current gain and to compensate for transmission delay.
2. Description of the Related Art
As integration density of semiconductor memory devices continues to increase, chip size also increases. Due to the increase in chip size, transmission rates of signals may be different depending upon differences in loading due to differences in physical lengths of signal lines. Different transmission rates of signals cause signal skewing, which in turn hinders the overall operating speed of a high-frequency semiconductor memory device.
FIG. 1 is a circuit diagram showing an output portion of a conventional semiconductor memory device. With reference to FIG. 1, data of memory cells coupled to a word line selected by a row address are transferred to data input/output lines by activation of a column selection signal selected by a column address. The data transferred to data input/output lines DIOi and DIOiB are output through an input/output sense amplifier (IOSA) to output lines FDOi and FDOiB. The data on the output lines FDOi and FDOiB are output through a driving circuit 10 to a data input/output pad DQ. The data to be output to the data input/output pad DQ is sampled in response to a predetermined sampling signal FRP in the driving circuit 10.
In a memory device having a plurality of memory blocks, IOSAs are arranged in a position which minimizes the difference between data input and output rates. However, distances from each memory block to the IOSA are typically different. Such a difference in the distance from each memory block to the IOSA causes load differences in signal lines which in turn causes IOSA data skew. To accommodate such data skew, data sampling period in the driving circuit 10 must be reduced. The reduction of the sampling period will be described with reference to the timing diagram of FIG. 2.
FIG. 2 is a timing diagram showing the reduction of a sampling period due to skew which has occurred between data input to the IOSA from a plurality of memory blocks. Here, an example of an ith memory block and a jth memory block, which is further away from the IOSA than the ith memory block, is described. Referring to FIG. 2, because the ith memory block is closer to the IOSA than the jth memory block, data read from the ith memory block is received by the IOSA earlier than data from the jth memory block. Thus, further considering a point in time where the data read from each memory block is sampled and input to a driving circuit 10, a point in time where data of the ith memory block is loaded onto the output line FDOi and a point in time where data of the jth memory block is loaded onto the output line FDOj are different.
The sampling signal FRP shown in FIG. 1, which is generated as a pulse signal, starts data sampling in synchronization with a leading edge of data which has last arrived at the IOSA and terminates the data sampling in synchronization with a trailing edge of data which has first arrived at the IOSA. Thus, as shown in FIG. 2, the sampling signal FRP has a sampling period corresponding to an overlapping period between the effective period of the jth memory block data FDOj and the effective period of the ith memory block data FDOi. The overlapping period is shorter than each effective period of the ith and jth memory block data FDOi and FDOj.
Thus, the sampling period of the sampling signal FRP is reduced by the skew between the data input to the IOSA from each memory block, the skew varying according to positions of memory blocks. In addition, such a reduction of the data sampling period may be a serious problem in a memory device which operates at a high frequency.